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circuit4u
circuit4u

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Play with RP2040 MCU PIO Assembler

using Rust pio-rs library — With the trend of ROE (Rust on Everything), cool kids (respectfully) have worked hard to port Rust Embedded toolchain to RP2040 MCU, in addition to many other MCUs already. After the ubiquitous Micro-Python (also Circuit-Python) and Arduino toolchains, Rust now becomes another development platform for Raspberry Pi Foundation’s RP2040 MCU…

Rust Programming Language

4 min read

Play with RP2040 MCU PIO Assembler
Play with RP2040 MCU PIO Assembler
Rust Programming Language

4 min read


Jun 25

Cross Two Clock Domains

Send Signal from a Faster to a Slower Clock Domain — 1. Slower to Faster Clock Domain It’s pretty straightforward to send signal from a slower clock domain to a faster clock domain. The basic assumption is that the faster clock can always capture the signal changes, i.e. the edge from low to high or high to low in the slower clock domain, provided that the metastability…

Fpga

3 min read

Cross Two Clock Domains
Cross Two Clock Domains
Fpga

3 min read


Jun 16

All your FPGA IO are belong to RP2040 PIO

PIO Assembly to Capture Key features of FPGA Verilog code — RP2040 MCU PIO has single clock cycle instruction sets and time delay syntax that make it easy to precisely control IO timing. It almost rivals FPGA in terms of IO control. …

Pio

3 min read

All your FPGA IO are belong to RP2040 PIO
All your FPGA IO are belong to RP2040 PIO
Pio

3 min read


May 29

Connect FTDI SPI with ICE40 FPGA

For bitstream configuration and SPI interface to PC — The open source toolchain for ICE40 FPGA works exceptionally well. For example, APIO (link) combines synthesis, simulation and programmer into one easy-to-use CLI, which makes ICE40 FPGAs fun to play with, in strong contrast to bulky, snail-slow Xilinx FPGA toolchains. 1. FTDI SPI Bitstream to Flash Chip Because of the free ICE40 open source toolchain, many low-price…

Rust

5 min read

Connect FTDI SPI with ICE40 FPGA
Connect FTDI SPI with ICE40 FPGA
Rust

5 min read


Apr 2

Rust Instrument Control with USB

where PyVISA can’t reach — The standard way to remote control or gather data from digital oscilloscope, DMM, signal generator, etc., is through GPIB/LAN/serial port at the back of these instruments, making connection to the PC. Once the hardware cable is connected, at software level, you need to install some quite large VISA runtime/library. Lastly…

Rust

4 min read

Rust Instrument Control with USB
Rust Instrument Control with USB
Rust

4 min read


Mar 24

Cross Compile Rust Code for Raspberry Pi

Use Pi as a headless data logger — 1. Goal Rust code was developed on the Windows PC for an experiment setup to collect and visualize real-time data from an embedded system (RP2040 MCU for example). Data is sent over serial/USB connection (FTDI 232H cable) to the PC. …

Raspberry Pi

3 min read

Cross Compile Rust Code for Raspberry Pi
Cross Compile Rust Code for Raspberry Pi
Raspberry Pi

3 min read


Mar 18

Rust LILYGO T-Display with RP2040

Piecing Together Embedded Rust Libraries — 1. Hardware LILYGO T-Display RP2040 (https://www.lilygo.cc/products/t-display-rp2040) LILYGO makes nice hardware modules that combine various TFT LCD displays with popular MCUs, such as ESP32 and RP2040. About two years ago, it introduced this T-display module that combines RP2040 (Raspberry Pi PICO) MCU with a ST7789V controlled 1.14" LCD display (135 x 240 pixels).

Rust

5 min read

Rust LILYGO T-Display with RP2040
Rust LILYGO T-Display with RP2040
Rust

5 min read


Aug 27, 2022

NeoPixel (WS2812) Bit Timing

The FSM Story — Inspired by Tim’s (blog link) FSM theory, I set out to measure a few different WS2812(B) neopixels in the draw. In my previous post (link), I described a 555 timer circuit with its CV (control voltage) pin adjustable via a secondary voltage source. The output pulse of the 555 timer…

Ws2812

4 min read

NeoPixel (WS2812) Bit Timing
NeoPixel (WS2812) Bit Timing
Ws2812

4 min read


Aug 22, 2022

Arbitrary Baud Rate Generator in Verilog

Explained with Japanese sōzu — A common FPGA design problem is to divide down a faster MHz external clock into 115200 or similar slower baud rate for serial communication use. Here are two links discussing such solutions: Controlling Timing within an FPGA Within an FPGA, everything is based upon event based timing. SPI controllers require a logic generated clock, I2C…zipcpu.com fpga4fun.com - Serial interface 2 - Baud generator Serial interface 2 - Baud generator Here we want to use the serial link at maximum speed, i.e. 115200 bauds (slower…www.fpga4fun.com

Verilog

5 min read

Arbitrary Baud Rate Generator in Verilog
Arbitrary Baud Rate Generator in Verilog
Verilog

5 min read


Aug 6, 2022

Play with 16x2 LCD Display

in Verilog Code — LCD display technology has been around for a long time, long before the advent of LCD TVs that have vibrant colors. In this article, we are focusing on this LCD1602 character LCD. LCD1602 (or HD44780 as one of its key components) has two rows, each of which can display 16…

Lcd Displays

5 min read

Play with 16x2 LCD Display
Play with 16x2 LCD Display
Lcd Displays

5 min read

circuit4u

circuit4u

189 Followers

memento of electronics and fun exploration for my future self

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