All your FPGA IO are belong to RP2040 PIO

PIO Assembly to Capture Key features of FPGA Verilog code

3 min readJun 16, 2023
PICO-ICE: both RP2040 and ICE40 FPGA

RP2040 MCU PIO has single clock cycle instruction sets and time delay syntax that make it easy to precisely control IO timing. It almost rivals FPGA in terms of IO control. It’s such a useful hardware feature, since RP2040 MCU is only a fraction of the cost and programming effort of a FPGA chip.

There are plenty of interesting examples (link) of using PIO, from driving NeoPixel to streaming VGA videos etc. In many cases, PIO assembly code captures key performance features that can only be expressed in Verilog/VHDL code on dedicated FPGA.

Here are some key features that PIO assembly code can do as well as FPGA Verilog code.

1. Control Timing

In FPGA, everything is driven from the main clock. To count down a fast main clock for LED toggling, one uses a counter

always @(posedge clk) begin
cnt <= cnt + 23'h1;

assign led_out = cnt[22];

So if the main clock clk runs at 125MHz, led_out toggles at about 7Hz.

In RP2040, you can divide down its 125MHz clock first, then use single clock instruction to toggle IO pin as well.

set pins, 1
set pins, 0




memento of electronics and fun exploration for my future self