Set New RP2040 System Clock Rate for PIO

With Internal PLL

Many RP2040 breakout boards come with a 12MHz external crystal. Inside RP2040, there are two PLLs, one sets a system clock rate at 125MHz, the other is at 48MHz for USB signals.

In my recent application, I need to use PIO to generate a 6.78MHz carrier frequency signal. The PIO instruction speed is one clock cycle. That clock can be exactly the system clock or a divide-down of the system clock. However it is hard to get exactly 6.78MHz from a 125MHz system clock.

To give a concrete example, 125MHz clock will run each PIO instructions at 8ns, so 18 * 8 = 144ns, which is closest to 1/6.78MHz = 147.5ns. But that’s not exact. BTW, the number 18 is easy to achieve with PIO “delays”, for example

 ".wrap_target",
 "set pins, 1 [8]", // total 18 cycles for 6.78MHz (147ns) carrier: 8ns * 18 = 144 ns
 "set pins, 0 [8]",
 ".wrap" 

Fortunately, one can change RP2040 system clock frequency by configuring the internal PLL with different dividers.

There is a Rust program (link) to do the PLL divider calculation for you, as long as you change this line to the desired PIO frequency. In my case, 67.8MHz:

    let desired_pio_frequency_hz = 67_800_000u64; //6_144_000u64;

Here is the print-out of the calculator program: vco freq = 1356 MHz, post divider 1 = 5; post divider 2 = 4; pio divider = 1