Port SmithForth to J1 CPU
Nowadays, one attractive feature of Forth language is that you can start from scratch and write your own Forth.
Not many programming languages can claim that, as Forth doesn’t need all the compiler and other layers of incidental complexity from traditional computer software.
One kind of DIY Forth is (for the initial part) written in assembly/machine code which is closest to the bare metal hardware.
A recent good example is David Smith’s SmithForth (link). It is written in Intel x86–64 CPU machine code and utilizes a few Linux API calls, to bootstrap itself from there.
In this article, we change the underlying CPU to J1 CPU, which is a Forth oriented CPU, with very concise Verilog implementation.
There already exists the original SwapForth, later Mercisp-ICE Forth, targeting J1 CPU, running on ICE40 FPGA. But in the spirit of DIY Forth, we are trying to port SmithForth to J1, in addition.
The idea is not to compare/compete which Forth is better, rather to show an example of how easy it is to roll your own Forth based on a few key Forth originated ideas.
Here is the list of topics to proceed:
