NeoPixel (WS2812) Bit Timing

The FSM Story



Inspired by Tim’s (blog link) FSM theory, I set out to measure a few different WS2812(B) neopixels in the draw.

In my previous post (link), I described a 555 timer circuit with its CV (control voltage) pin adjustable via a secondary voltage source. The output pulse of the 555 timer is fed into DIN pin of a neopixel. That makes a very simple test circuitry, no MCU, no programming.

By adjusting the voltage at the CV pin, you control the pulse width (duty cycle) of repeating pulse outputs. At the same time, once that pulse output is connected to DIN of the neopixel, DOUT pin of the neopixel will try to relay the digital ONE or ZERO signal downstream, from which you can measure and tell if you are sending digital ONE or ZERO to the internal circuitry of the neopixel.

In each of these scope plots below, the top yellow trace is DIN signal, the bottom trace is DOUT signal, and the time division is 100ns.

I’ve included Tim’s FSM timing diagram for reference:

Neopixel First Set

digital ZERO
digital ONE

A few points:

  1. looking at DOUT signals: digital ONE = 680ns is exactly twice longer than digital ZERO = 340ns
  2. since digital ZERO = 2 CLK-cycle: CLK-cycle = 170ns
  3. 200ns delay between top yellow and bottom trace could be explained by 1 CLK-cycle + internal oscillator start-up time
  4. to send digital ZERO: as long as the top yellow trace is shorter than 200 + 2 CLK-cycle = 200 + 340ns, internal FSM will sample zero after this 540ns
  5. simlarily if the top yellow trace is higher, longer than 540ns, internal FSM will sample a digital HIGH, thus keeping the bottom trace high for two more CLK-cycles (4 CLK-cycles in total).

This set of neopixels match Tim’s FSM diagram almost exactly. DOUT signal is completely CLK driven. And because DOUT is determined…




memento of electronics and fun exploration for my future self