Connect FTDI SPI with ICE40 FPGA
The open source toolchain for ICE40 FPGA works exceptionally well. For example, APIO (link) combines synthesis, simulation and programmer into one easy-to-use CLI, which makes ICE40 FPGAs fun to play with, in strong contrast to bulky, snail-slow Xilinx FPGA toolchains.
1. FTDI SPI Bitstream to Flash Chip
Because of the free ICE40 open source toolchain, many low-price development board has spun up around ICE40 FPGAs. Most of them use FTDI FT232H in SPI mode to write bitstream to a Flash chip, which then in turn configures the ICE40 FPGA.
For example, in Upduino 3.1 schematic
FT232H has its SPI signals going into the Flash chip to send ICE40 bitstream. The bitstream is then read into ICE40 via its SPI lines (see schematic snippets below) for configuration upon FPGA power up.
In this case, the Flash chip serves as a SPI slave, whereas both FTDI and ICE40 serve as SPI masters.
2. FTDI SPI to ICE40 for configuration
In addition to that, FTDI can write bitstream over SPI to ICE40 directly (called SRAM program), in which case FTDI is still a SPI master, but ICE40 acts as a SPI slave. (Lattice configuration application notes)
To enable this in Upduino, some 0-Ohm resistors needs to be re-soldered, to redirect
FTDI_MOSI to ICE40
FPGA_SO. If you have Lattice ICE40 breakout board , just change the jumper orientation on the PCB.
On the software side, we no longer use APIO (
upload) command to write the bitstream to Flash. Instead, we can use the following code snippet to upload the bitstream (from a bin file) to ICE40 using FTDI D2XX MPSSE SPI mode directly.
On the Windows machine, that means we don’t need Zadig to swap FTDI D2XX native driver to
libusbk driver any more. The benefit is that once ICE40 is configured, the exact same SPI port can be re-used for your FPGA application to communicate with the…