Arbitrary Baud Rate Generator in Verilog

Explained with Japanese sōzu



A common FPGA design problem is to divide down a faster MHz external clock into 115200 or similar slower baud rate for serial communication use.

Here are two links discussing such solutions:

In addition, my favorite solution is James Bowman’s arbitrary baud rate generator code. However his specific web page with explanation is no longer available online.

In this article, I will try to reason out the principle behind an arbitrary baud rate generator.

For example, your FPGA PCB comes with a 12MHz external clock oscillator. But the Verilog serial TX module needs 115200 baud rate clock, and RX module needs 115200 x 2 clock (twice TX rate) to sample data.

Since 12_000_000 / 115200 is not an integer, a simple counter == INT_N method won’t work.

In fact, to simplify, the ratio 12_000_000 / 115200 = 625/6, which means as the faster clock runs 625 cycles, the slower clock only runs 6 cycles.

We can count 625 cycles easily, driven by 12MHz clock, but how to generate 6 cycles determining the slower clock, in the same period.

Maybe we can draw some inspiration from Japanese sōzu. The idea has two parts:

  1. count with an integer larger than 1
  2. empty out the counter when filled

To illustrate, let’s start with a simpler ratio, for example 9/4. In other words, every 9 cycles of faster clock, the slower clock needs to tick 4 times.

To accomplish that, imagine you are filling a 9 gallon container with 4 gallon water jar.

9-gallon container starts empty.

  1. drop 4 gallon of water; fill = 4
  2. drop 4 gallon of water; fill = 8
  3. drop 4 gallon of water; now since the container…




memento of electronics and fun exploration for my future self