Arbitrary Baud Rate Generator in Verilog

Explained with Japanese sōzu

A common FPGA design problem is to divide down a faster MHz external clock into 115200 or similar slower baud rate for serial communication use.

Here are two links discussing such solutions:

Controlling Timing within an FPGA

fpga4fun.com - Serial interface 2 - Baud generator

In addition, my favorite solution is James Bowman’s arbitrary baud rate generator code. However his specific web page with explanation is no longer available online.

In this article, I will try to reason out the principle behind an arbitrary baud rate generator.

For example, your FPGA PCB comes with a 12MHz external clock oscillator. But the Verilog serial TX module needs 115200 baud rate clock, and RX module needs 115200 x 2 clock (twice TX rate) to sample data.

Since 12_000_000 / 115200 is not an integer, a simple counter == INT_N method won’t work.

In fact, to simplify, the ratio 12_000_000 / 115200 = 625/6, which means as the…